1. Field of the Invention
A test scheme is invented for testing Analog-to-Digital Converters (ADCs). In this scheme, a system clock pulse is used to drive an n+m-bit counter and the frequency, duty cycle and amplitude of the system clock pulse is regulated to become a regulated clock signal that is integrated by an Integrator to form a called step-ramp signal as a test stimulus, where n is the resolution of the ADC under test and m=1, 2, 3 . . . , based on the desired accuracy of the test scheme. With this design, the step-ramp stimulus can correctly synchronize with the n+m-bit counter whose output codes provide the references for testing the n-bit ADC. The Test Response Analyzer can be designed with completely digital circuits to analyze the output codes of the ADC and the counter for identifying whether the specific parameters of the ADC are within acceptable ranges.
On the other hand, the step-ramp stimulus is divided into several segments. Various segments are generated by the integrations of the regulated clock signal with different duty cycles. Gradually increasing duty cycles for integrations compensates the nonlinearly rising linkage currents depending on rising voltages of the segments. The main characteristics of the proposed test scheme include:    1. The design of the high accurate step-ramp signal as a test stimulus for testing Analog-to-Digital converters.    2. The design of the compensation mechanism of linkage current with enlarging duty cycle for integration.    3. The design of correct synchronization between the stimulus and outputs of the reference counter.    4. The design of the Test Response Analyzer with completely digital circuits.
2. Description of the Prior Art
With advanced technologies of IC design and manufacture, a complex mixed-signal system circuits which includes digital, analog and interface parts are integrated in a chip. High complex designs make the difficulty in chip testing. As a result, chip testing cost has drastically increased and may exceed the design cost. One of most effective solutions is by the process of design for testability (DFT) which refers to the design efforts to ensure that the circuits in a chip are easily testable. In mixed-signal chips, Analog-to-Digital converters (ADCs) and Digital-to-Analog converters (DACs) are important devices to work as interfaces between digital and analog circuits. The qualities of converters dominate the performances of mixed-signal chips. How to develop DFT techniques for testing converters has become an important issue.
The converters are usually tested by examine whether the values of dynamic and static parameters are within acceptable ranges. In general, dynamic parameters contain Settling Time, Signal-to-Noise Ratio (SNR), Total Harmonic Distortion (THD) and Effective Number of Bits (ENOB). Static parameters include Offset Error, Gain Error, Integral Non-linearity (INL) and Differential Non-linearity (DNL). For detecting parameters, a test scheme mainly contains a test signal generator to produce test stimuli, a reference signal generator to produce references and a test response analyzer to identify the values of parameters whether they are within acceptable ranges.
For testing dynamic parameters, sine or triangle wave which is cyclic signal is usually used as a test stimulus in the scheme. For analyzing dynamic parameters based on cyclic test signal, this scheme needs a high performance CPU to do complex calculation and memory space for data storage during calculation. The calculation performs Fourier Transform analyses to extract out parameters. If the scheme is implemented in chips to become a Built-In Self-Test structure, the test signal generator for generating cyclic signals, CPU and memory exhaust large chip area. Therefore the analyses of dynamic parameters are preferred to be done by external instruments to save chip area.
When testing static parameters, highly accurate stimuli, reference signals and a specific Test Response Analyzer are designed in the scheme. Multiple discrete stage, continuous ramp down or continuous ramp up signals are used as test stimuli in the scheme. The reference signals can be defined by the outputs of the ideal ADC with ideal input stimuli. The Test Response Analyze performs the comparisons between the reference signals and the outputs of ADC under test. However, for high resolution ADC testing, multiple high accurate stage stimuli (2n stimuli for n-bit ADCs) are difficult to be implemented in the chip because they exhaust large chip area. Meanwhile, switching the reference stimuli via analog switches generates noises and spikes that influence the accuracy of reference stimuli. Therefore it cannot be applied in the chip for high resolution converter testing.
Another embodiment is to apply increasing or decreasing ramp signals as test stimuli. The ramp signal is always generated by an integrator. The linearity of the signal is greatly affected by the leakage current of the capacitor in the integrator. This drawback greatly influences the accuracy of the test scheme. Therefore, the ramp signals are usually used as test stimuli for testing low resolution ADCs less than 10 bits.
FIG. 1 is a perspective view of ADC's static parameter testing of prior art. Wherein the test signal generator (A1) generates multiple voltages (Vin) as test stimuli that are inputted to the ADC under test (A2). Then the outputs of A2 are connected to a Digital-to-Analog converter (DAC) (A3). The DAC converts the digital outputs of the ADC into analog signals. A comparator A4 compares the input voltage Vin with the output voltage (Vout) of the DAC and analyzes comparison results. The main issues in this scheme are the necessity of the DAC that always has higher resolution than that of the ADC. If this scheme is implemented with Built-In Self-Test designs, the test signal generator and the DAC will exhaust large chip area.
The qualities of converters dominate the performances of mixed-signal chips. Researchers and engineers make efforts to develop effective test schemes to examine converter qualities. The topic of developing test scheme for testing converters has become a specific research filed. Thus, to have an improved test scheme and method thereof of converters gives resolutions of chip testing issues.